7.1 Parity Generator Cell

In this section you will be required to generate a Parity Generator cell from scratch. The cell is implemented mainly in NMOS pass logic. From a circuit diagram, you will generate a suitable stick diagram, simulate it using SPICE and produce full custom layout.

Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd number of ones. If the data word contains an even number of ones then the output of the parity generator will be low. By concatenating the Parity bit to the dataword, a word will be formed which always has an even number of ones i.e. has even parity.

Parity is used on communication links (e.g. Modem lines) and is often included in memory systems.

DATAWORD  EVEN O/P ODD O/P 00000000 0 1 10000000 1 0 00010000 1 0 11101001 1 0

If a dataword is sent out with even parity, but has odd parity when it is received then the data has been corrupted and must be resent. As its name implies the operation of an Odd Parity generator is similar but it provides odd parity. The table shows the parity generator outputs for various 8-bit data words.

Parity Generation

A circuit which could be used to generate even parity for 4-bit data is shown on the left.

If this approach is adopted for 16 or 32 bit data busses the resultant circuit would be large, with complex interconnect. A more satisfactory approach for a VLSI implementation is to use a linear architecture as shown below.

VLSI Approach - Use N 1-bit cells:

In this approach a one-bit cell is designed which can be used to form an n-bit circuit. In the circuit shown below, each cell is identical, with a 1,0 pair fed in from the left hand side and one bit of the data word fed in from below. A 1,0 pair passes out of the right hand edge of the cell into the left hand side of the next cell. If the data input is low, the 1,0 pair pass through the cell unaltered. If the input is high the the 1,0 pair is swapped (i.e. becomes 0,1)

Thus when all data inputs are low then X=0 and Y=1.
If one data input is high then X=1 and Y = 0
If two data inputs are high then X=0, Y=1 and so on
ie for an odd number of 1s: X=1, for an even number of 1s: X=0.